Kumar Yelamarthi
Kumar Yelamarthi
Assistant Professor
Electrical and Computer Engineering

ET Building 130B
989-774-7164
kumar.yelamarthi@cmich.edu

Web site: Circuits and Systems Exploration (CASE) Lab

Education

Ph.D., Electrical Engineering, Wright State University, Dayton, OH
M.S., Electrical Engineering, Wright State University, Dayton, OH
B.E., Instrumentation & Control Engineering, University of Madras, India

Affiliations

Institute of Electrical and Electronics Engineers (IEEE); American Society for Engineering Education (ASEE); National Society of Professional Engineers (NSPE)

Professional Interests

VLSI, FPGA, integrated circuit design, CAD tool development, digital design automation, autonomous adaptive systems, applied electronics, MEMS, Engineering Education

Teaching Areas

Digital design, VLSI systems, analog and mixed-signal circuits, microprocessors, freshman programs, interdisciplinary senior design projects

Honors and Awards

  • 2008 Global Citizen Award, Wright State University
  • Outstanding Technical Director, American Society for Engineering Education North Central Section, March 2008
  • 2nd Best Student Paper Award, 2008 American Society for Engineering Education North Central Section Conference
  • 2004-05 WSU-CECS Excellence in Teaching Award for Graduate Teaching Assistants
  • 2003-04 WSU-CECS Dean’s Award for Excellence in Academics, Leadership, and Service to College
  • Member, Tau Beta Pi Engineering Honor society
  • Member, Omicron Delta Kappa National Leadership Honor Society

Selected Publications and Presentations

  • K. Yelamarthi and C-I. H. Chen, “A Path Oriented In Time Optimization Flow for Mixed-Static-Dynamic CMOS Logic,” 51st IEEE Midwest Circuits and Systems Conference, August 2008
  • K. Yelamarthi and C-I. H. Chen, “Process Variation Aware Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization,” Journal of Computers, Academy Publishers, vol.3, no.2, pp.21-28, 2008 (invited journal)
  • K. Yelamarthi and C-I. H. Chen, “Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic,” IEEE International Symposium on Quality Electronic Design, March 2008
  • P. R. Mawasha and K. Yelamarthi, “Project Management in an Interdisciplinary Senior Design Team,” ASME International Mechanical Engineering Congress and Exposition, November 2007
  • P. R. Mawasha, K. Yelamarthi, M. Wolff, J. Slater, and Z. Wu, “An Integrated Technology Project and its Potential Impact on Interdisciplinary Undergraduate Engineering Experience,” 114th Annual ASEE Conference & Exposition, June 2007
  • K. Yelamarthi and C-I. H. Chen, “A Sub-nanosecond Low-Power High-Performance 64-bit Adder,” IEEE International Conference on Computers and Devices for Communication, December 2006

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